The present invention generally relates to a semiconductor device and a method for fabricating the device. More particularly, the present invention relates to a semiconductor device, in which an electronic device has been formed out of a multilayer structure, including a ferroelectric film, on an insulating film deposited over a pattern of electrodes or interconnects, and to a method for fabricating the device.
An electronic device formed out of a multilayer structure including a ferroelectric film, e.g., a ferroelectric capacitor including a capacitive insulating film made of a ferroelectric material, not only has a high dielectric constant but also shows hysteresis with residual electric polarization. Accordingly, in the fields of capacitors with large capacitance and nonvolatile memories, those capacitors including a ferroelectric film have recently been replacing the known capacitors including a capacitive insulating film of silicon dioxide or silicon nitride.
Hereinafter, a known method for fabricating a semiconductor device (which will be herein called a xe2x80x9cfirst prior art examplexe2x80x9d for convenience sake) will be described with reference to FIGS. 8(a) through 8(e).
First, as shown in FIG. 8(a), an interconnect (or gate electrode) 11 of polysilicon with a thickness of 400 nm, for example, is formed on a semiconductor substrate 10, in which a diffused layer for an MOS transistor, for example, has been defined. Next, a silicon nitride film 12 is deposited to a thickness of 40 nm, for example, over the entire surface of the substrate 10 as well as over the interconnect 11. Then, an interlayer dielectric film 13, which may be a first silicon dioxide film doped with boron and phosphorus, is deposited to a thickness of 1000 nm, for example, over the silicon nitride film 12.
Subsequently, as shown in FIG. 8(b), a resist film 14 is deposited on the interlayer dielectric film 13 so that the surface of the film 14 becomes as flat as possible. Then, the resist film 14 and interlayer dielectric film 13 are etched back, thereby planarizing the surface of the interlayer dielectric film 13 as shown in FIG. 8(c).
Thereafter, as shown in FIG. 8(d), first metal film 14, ferroelectric film 15 and second metal film 16 are deposited in this order on the interlayer dielectric film 13 with the planarized surface. In this case, the first and second metal films 14 and 16 may be both made of platinum. Examples of known techniques for depositing the ferroelectric film 15 include sputtering, metalorganic chemical vapor deposition (MOCVD) and spin coating. Among these techniques, the spin coating technique is advantageous in uniformity of film thickness and quality, stability of conditions and productivity. In a spin coating process, the ferroelectric film 15 is formed by coating the surface of an underlying layer with an organometallic solution, containing the constituent metal of the ferroelectric film 15, using a coater, and then annealing and crystallizing the resultant coating at an elevated temperature. In this process, the coating is formed using a coater. Thus, the thickness of the resultant ferroelectric film 15 is much affected by the unevenness of the underlying layer. Specifically, part of the ferroelectric film 15, covering the upper corners of a stepped portion, will be relatively thin, while another part of the ferroelectric film 15, covering the lower corners of the stepped portion will be relatively thick. Accordingly, to uniformize the thickness of the ferroelectric film 15, the surface of the interlayer dielectric film 13 should be as flat as possible.
Next, as shown in FIG. 8(e), the second metal film 16, ferroelectric film 15 and first metal film 14 are dry-etched and patterned in this order, thereby forming a capacitor made up of upper electrode 16A, capacitive insulating film 15A and lower electrode 14A. In this step, parts of the interlayer dielectric film 13, on which the capacitor does not exist, is over-etched through the dry etching process. As a result, a patterned interlayer dielectric film 13A is obtained.
Subsequently, although not shown, a second silicon dioxide film is deposited to a thickness of 200 nm, for example, over the entire surface of the semiconductor substrate 10 as well as over the respective regions where the MOS transistor and the capacitor will be formed. Then, a contact hole is opened through respective parts of the second silicon dioxide film and the patterned interlayer dielectric film 13A, in which the MOS transistor will be formed. Thereafter, the contact hole is filled in with a conductor film, thereby forming a contact connected to the MOS transistor.
The multilayer structure, consisting of the second metal film 16, ferroelectric film 15 and first metal film 14, includes the ferroelectric film 15, which is dry-etched at a low rate because the film 15 contains a metal that has a high melting point. Accordingly, the multilayer structure is also dry-etched at a relatively low rate. In other words, the dry-etch selectivity of the multilayer structure to the interlayer dielectric film 13 becomes low.
Thus, in the dry etching process for forming a capacitor made up of the upper electrode 16A, capacitive insulating film 15A and lower electrode 14A, the interlayer dielectric film 13 is over-etched so deep, except for its part on which the capacitor will be formed. As a result, the interconnect 11 is also partially etched away unintentionally as shown in FIG. 8(e). Particularly if some dopants such as boron and phosphorus have been added to the silicon dioxide film to further planarize the interlayer dielectric film 13 by a reflow process, the dry-etch rate of the interlayer dielectric film 13 will further increase. That is to say, the etch selectivity of the multilayer structure to the interlayer dielectric film 13 will further decrease in that case. Consequently, the above problem will get even more noticeable.
To solve such a problem, an alternative method for fabricating a semiconductor device (which will herein be called a xe2x80x9csecond prior art examplexe2x80x9d for convenience sake) was suggested. Hereinafter, this method will be briefly described with reference to FIGS. 9(a) through 9(c).
Specifically, a relatively thick interlayer dielectric film 13, which is a silicon dioxide film containing boron and phosphorus, is deposited to a thickness of about 1500 nm, for example, over the silicon nitride film 12 and then has its surface planarized as shown in FIG. 9(a). Next, as shown in FIG. 9(b), the first metal film 14, ferroelectric film 15 and second metal film 16 are deposited in this order on the interlayer dielectric film 13 with the planarized surface. Then, the second metal film 16, ferroelectric film 15 and first metal film 14 are dry-etched and patterned in this order, thereby forming a capacitor consisting of the upper electrode 16A, capacitive insulating film 15A and lower electrode 14A as shown in FIG. 9(c). According to this alternative method, the interlayer dielectric film 13 also has its thickness reduced or over-etched, except for its part on which the capacitor will be formed, during the dry etching process. As a result, a patterned interlayer dielectric film 13B is obtained.
In this second prior art example, however, the interlayer dielectric film 13 is relatively thick, so is the patterned interlayer dielectric film 13B. Thus, a contact hole to be formed in that interlayer dielectric film 13B will have a greater aspect ratio. In that case, the metal film to fill the contact hole will have decreased step coverage, i.e., the contact hole cannot be covered with a metal film satisfactorily. As a result, problems of different types, e.g., disconnection or increase in contact resistance, newly arise. Accordingly, it is not preferable to increase the thickness of the interlayer dielectric film 13 excessively.
It is therefore an object of the present invention to prevent electrodes or interconnects, which are located under an interlayer dielectric film, from being exposed even if the interlayer dielectric film, deposited under a multilayer structure including a ferroelectric film, has its thickness reduced.
To achieve the above object, a first inventive method for fabricating a semiconductor device includes the steps of: a) forming a pattern of electrodes or interconnects on a semiconductor substrate; b) depositing a first insulating film, which will be dry-etched at a relatively high rate and exhibit relatively high planarity, over the substrate as well as over the pattern; c) depositing a second insulating film, which will be dry-etched at a relatively low rate and exhibit relatively low planarity, over the first insulating film; and d) forming a multilayer structure, including a ferroelectric film, on the second insulating film and then dry-etching and patterning the multilayer structure, thereby forming an electronic device out of the multilayer structure.
According to the first method, the first insulating film, which will exhibit relatively high planarity, is deposited over the substrate as well as over the pattern. Thus, the surface of the first insulating film is sufficiently flat and is not affected so much by the unevenness of the pattern located under the first insulating film.
Also, the second insulating film, which will be dry-etched at a relatively low rate, is deposited on the first insulating film, which will be dry-etched at a relatively high rate. Then, the multilayer structure, including the ferroelectric film, is formed on the second insulating film and then dry-etched and patterned, thereby forming the electronic device out of the multilayer structure. Accordingly, the ratio of the dry-etch rate of the multilayer structure to that of the second insulating film increases. That is to say, the dry-etch selectivity of the multilayer structure to the second insulating film gets high, so the second insulating film is harder to etch. Thus, even if the total thickness of the interlayer dielectric film, consisting of the first and second insulating films, is reduced, the pattern of electrodes or interconnects is not exposed.
In one embodiment of the present invention, the first method preferably further includes the steps of: depositing a wet-etch stopper over the pattern between the steps a) and b); and wet-etching the first insulating film to reduce the thickness of the first insulating film between the steps b) and c).
As described above, in a dry etching process carried out to form an electronic device (e.g., a capacitor), the interlayer dielectric film is often over-etched. That is to say, a big level difference is created between a part of the interlayer dielectric film on which the electronic device (or capacitor) will be formed and the other parts thereof (e.g., a part in which an MOS transistor will be formed). Accordingly, when a lithographic process is carried out to define interconnects on the interlayer dielectric film, a focus error is likely to occur. As a result, several interconnects might be bridged together unintentionally or some interconnects might be disconnected.
However, if the second insulating film is deposited after the first insulating film has been wet-etched to reduce the thickness thereof, then the level difference between the part of the interlayer dielectric film on which the electronic device will be formed and the other parts thereof will decrease. Accordingly, in the lithographic process for defining interconnects on the interlayer dielectric film, a focus error is much less likely to occur. As a result, almost no interconnects will be neither bridged together nor disconnected unintentionally.
In another embodiment, the first method preferably further includes the steps of: depositing a wet-etch stopper over the pattern between the steps a) and b); and wet-etching and removing parts of the second insulating film, on which the electronic device does not exist, after the step d) has been performed.
By wet-etching and removing parts of the second insulating film, on which the electronic device does not exist, part of the interlayer dielectric film (consisting of the first and second insulating films), on which the electronic device does not exist (e.g., a part in which an MOS transistor will be formed) can have its thickness further reduced. Thus, the aspect ratio of a contact hole, which will be formed in the interlayer dielectric film, can be reduced and the step coverage for the contact hole can be further improved.
In still another embodiment, the first insulating film is preferably a first silicon dioxide film containing a dopant, while the second insulating film is preferably a second silicon dioxide film containing substantially no dopants.
A second inventive method for fabricating a semiconductor device includes the steps of: forming a pattern of electrodes or interconnects on a semiconductor substrate; depositing a wet-etch stopper film over the substrate as well as over the pattern; depositing an insulating film over the wet-etch stopper film; forming a multilayer structure, including a ferroelectric film, on the insulating film and then dry-etching and patterning the multilayer structure, thereby forming an electronic device out of the multilayer structure; and selectively wet-etching the insulating film so that parts of the insulating film, on which the electronic device does not exist, will have a reduced thickness.
The second method includes the step of selectively wet-etching parts of the insulating film, on which the electronic device does not exist, to reduce the thickness of those parts. Accordingly, the insulating film can have its thickness reduced without damaging the pattern of electrodes or interconnects.
In one embodiment of the present invention, the insulating film preferably includes a silicon dioxide film containing a dopant.
In the first or second method of the present invention, the electronic device may be a capacitor including a capacitive insulating film that has been formed out of the ferroelectric film.
A first inventive semiconductor device includes: a pattern of electrodes or interconnects formed on a semiconductor substrate; a first insulating film deposited over the substrate as well as over the pattern, the first insulating film having been dry-etched at a relatively high rate and exhibiting relatively high planarity; a second insulating film deposited over the first insulating film, the second insulating film having been dry-etched at a relatively low rate and exhibiting relatively low planarity; and an electronic device formed on a part of the second insulating film, under which the pattern does not exist, out of a multilayer structure including a ferroelectric film.
In the first semiconductor device, the first insulating film, exhibiting relatively high planarity, has been deposited over the substrate as well as over the pattern. Thus, the surface of the first insulating film is sufficiently flat and is not affected so much by the unevenness of the pattern located under the first insulating film.
Also, the second insulating film, which has been dry-etched at a relatively low rate, is deposited on the first insulating film, which was dry-etched at a relatively high rate. And the electronic device has been formed on the second insulating film out of the multilayer structure including the ferroelectric film. Accordingly, the ratio of the dry-etch rate of the multilayer structure to that of the second insulating film increases. That is to say, the dry-etch selectivity of the multilayer structure to the second insulating film gets high, so the second insulating film is harder to etch. Thus, even if the total thickness of the interlayer dielectric film, consisting of the first and second insulating films, is reduced, the pattern of electrodes or interconnects is not exposed.
In one embodiment of the present invention, parts of the second insulating film, on which the electronic device does not exist, have preferably been wet-etched and removed.
In such an embodiment, the part of the interlayer dielectric film (consisting of the first and second insulating films), on which the electronic device does not exist (e.g., a part in which an MOS transistor will be formed) can have its thickness further reduced. Thus, the aspect ratio of a contact hole, which will be formed in the interlayer dielectric film, can be reduced and the step coverage for the contact hole can be further improved.
In another embodiment of the present invention, the first insulating film is preferably a first silicon dioxide film containing a dopant, while the second insulating film is preferably a second silicon dioxide film containing substantially no dopants.
A second inventive semiconductor device includes: a pats tern of electrodes or interconnects formed on a semiconductor substrate; an insulating film deposited over the substrate as well as over the pattern; and an electronic device formed on a part of the insulating film, under which the pattern does not exist, out of a multilayer structure including a ferroelectric film. In the second inventive device, parts of the insulating film, on which the electronic device does not exist, have been wet-etched and removed.
In the second semiconductor device, parts of the insulating film, on which the electronic device does not exist, have been wet-etched and removed to reduce the thickness thereof. Thus, the thickness of the insulating film can be reduced without damaging the pattern of electrodes or interconnects.
In one embodiment of the present invention, the insulating film preferably includes a silicon dioxide film containing a dopant.
In the first or second semiconductor device, the electronic device may be a capacitor including a capacitive insulating film that has been formed out of the ferroelectric film.